1. Field of the Invention
The present invention relates to a high voltage MOS-gated power device, and to a related manufacturing process.
2. Discussion of the Related Art
MOS-gated power devices with breakdown voltages between 300 and 1000 V have a high output resistance (or “on” resistance) due mainly to the epitaxial drain layer resistance that is necessary for the high voltage applied, and depends on the doping concentration of the epitaxial layer itself.
On the other hand, if, in the attempt to increase the integration density it is desired to reduce the distance between the elementary functional units (cells or stripes) without increasing the output resistance of the MOS-gated power device, it is necessary to increase the doping concentration of the common drain layer. This, however, results in a reduction of the breakdown voltage of the MOS-gated power device.
In order to obtain MOS-gated power devices with a low output resistance and a high breakdown voltage, it is possible to produce power devices with drain layers comprising many sub-layers with different doping concentrations (MultiDrain devices, MDMOS).
Another known technique is described in U.S. Pat. No. 5,216,275 and in U.S. Pat. No. 5,438,215, wherein the common drain layers beneath the body regions of the elementary functional units are constituted by columns of the N conductivity type, alternated to body “pockets” of the P conductivity type. The above-mentioned structure is obtained by a manufacturing process comprising trench etching and filling steps, and such a process is very complex because the drain thickness is comprised between 20 and 100 μm whereas the width of the cells or stripes is about 5–10 μm.
In view of the state of the art described, it is an object of the present invention to provide a high voltage MOS-gated power device with a low output resistance.